Last modified: Mon Jun 22 08:35:20 UTC+0200 2026 © A. Tarpai
Intel 386 Essential: the 32-bit IA-32
Intel's first ever 32-bit CPU, the 80386 (1985) was designed to be binary compatible with the large 8086 code base already existing. Also, with the 286 p-mode-addition to run 16-bit protected system code unaltered.
The 386 has full 32-bit architecture: registers, operands, data movements, addresses are all 32-bit. The CPU has 32 physical data- and address lines.
But it is both a 32- and a 16-bit CPU at the same time. 16-bit operation is not a distinct operation mode. Instead, the 386 has an architecture and hardware model that can fully emulate the 16-bit 8086 operation.
The 386 defines new 32-bit addressing modes: a new MODR/M byte format with optional SIB byte to encode 32-bit address offsets of [BASE-REGISTER + INDEX-REGISTER * SCALE + DISP32]. Register usage is almost general. Legacy 16-bit MODR/M byte interpretation and 16-bit offset is still emulated – see Addressing Modes.
The 32-bit CPU hardware model
Based on the 286 hw model: the 386 is a direct extension of the 16-bit 286 on the hardware level with full backward compatibility.
4GB RAM
+-----------+
| |
| |
| |
| | 32-bit
32-bit | 4GB | <-- EA OFFSET
segment | |
base -----> +-----------+
| |
| |
32-bit 386 CPU PROTECTION | |
+----------------------+--------------+------------------|---+ | |
| | on-chip SR | | | | |
| | ________ | ______________ _|_ | | |
| 32-bit registers | |___CS___|-|-|______________|___| | | |
| | |___DS___|-|-|______________|___| | | |
| | |___SS___|-|-|______________|___| | | |
| | |___ES___|-|-|______________|___| | | |
| | |___FS___|-|-|______________|___| | | |
| 32-bit instr OFFS --|-> |___GS___|-|-|______________|___| | -----/---> | |
| | 16-bit | 32-bit base | 32-bit | |
| | | | address | |
+----------------------+--------------+----------------------+ +-----------+
The addition is two new user-programmable Data Segment Registers FS/GS. The CPU never uses these after setting up their Descriptor Cache on hardware-reset.
32-bit memory reference principles
Just as the 8086, every memory reference (including code fetch, implicit stack operations) use one of the implied or overridden SR to add a BASE value to the computed instruction offset.
The adder is 32-bit wide adding 32-bit offsets to a 32-bit base, addressing 4GB space.
386 PHYSICAL ADDRESS PATH
from instructions
addressing modes DESCRIPTOR CACHE
+---------------+ +---------------+---------------+------+
| 32-BIT OFFS | | 32-BIT BASE | 32-BIT LIMIT | ATTR |
+---------------+ +---------------+---------------+------+
| |
LIMIT/ACCESS |
CHECK |
| |
| 32-bit adder |
| ___ |
+----------/ + \----------+
\___/
|
|
32-BIT PHYSICAL
ADDRESS*
* Still virtual when paging enabled
For EVERY memory reference, this BASE value stored in the Descriptor Cache is used for all memory access as the actual segment base.
This mechanism is always ON: adding SR base and limit/access check, exceptions cannot be turned off and is always in effect – also in Real Mode, when the PE-bit is cleared. Memory access behaves based on attribute bits stored in the Descriptor Cache. Writing SR will load values in the cache.
Flat or Linear memory model
Instructions can fully address the whole 4GB address space. SR BASE is not needed for address-space extension, but the segmented memory model is still there to help modular programming – and protection (limit/access check).
Although segmentation cannot be turned off, there is a possibility to address 4GB flat memory by setting segment bases to zero.
Protected-mode hardware- and programming model
Same as 286 Protected-mode. But every base-address in registers, data-structures are extended to 32-bit.
Similar to the 286, every SR has an associated Descriptor Cache, but holding a 32-bit SEGMENT BASE, 32-bit SEGMENT LIMIT and additional ATTRIBUTE bits for 16/32-bit operation:
386 ATTR BITS 286 ACCESS RIGHT BYTE
<-------------> <----------------------------->
+---+---+---+---+ +---+---+---+---+---+---+---+---+
| G |D/B| 0 | V | | P | DPL |S=1| X |C/E|R/W| A |
+---+---+---+---+ +---+---+---+---+---+---+---+---+
|
|
The D-bit is a CS attribute: for 16/32-bit data-size and addressing modes
The B-bit is a SS attribute: for 16/32-bit SP/ESP addressing for stack references
See Descriptors.
16/32-bit CPU operation
The two most important setting that determines 16/32-bit CPU operation is the PE-bit and the D-bit (see Addressing Modes). These two are unrelated and gives possibilities for different modes:
| CS DESCRIPTOR CACHE D-bit | |||
|---|---|---|---|
| D=0 | D=1 | ||
| 386 runs 16-bit code1 | 386 runs 32-bit code1 | ||
| PE = 0 | 16-bit IVT Interrupts | 8086 emulation3 | bootstrap bare metal programming |
| 8086 SR write | |||
| RM Exceptions | |||
| PE = 1 | 16/32-bit2 IDT Interrupts | 286 protected emulation | full 32-bit protected operation |
| SR write is Selector | |||
| Protection Exceptions | |||
| 1 16/32-bit code still can be overridden on a per-instruction-basis using 66/67h prefixes 2 Based on 16/32-bit GATE format 3 8086 emulation but with new instructions available, new addressing modes and 32-bit data movements with 66/67h prefix | |||
New instructions
Note that 32-bit instructions does not exists: the 386 interprets the same opcodes as 32-bit instructions.
| New instructions introduced by 80386 | ||
|---|---|---|
| 66/67 operand-size/addressing mode prefix | 66/67h | |
| FS/GS segment override | 64/65h | |
| PUSH/POP FS/GS instructions | 0F | |
| LFS, LGS instructions | 0F | |
| LSS: atomic load of SS:REG | LSS [mem] | 0F |
| Long-displacement conditional jumps | Jcc rel32 | 0F |
| Single-bit instructions | BTx r/m, reg/imm | 0F |
| Bit scan | BSF/BSR reg, r/m | 0F |
| Double-shift instructions | SHLD/SHRD | 0F |
| Byte set on condition | SETcc | 0F |
| Move with sign/zero extension | MOVZX/MOVSX | 0F |
| Generalized multiply | IMUL reg, r/m | 0F |
| MOV to and from control registers | 0F | |
| MOV to and from test registers | 0F | |
| MOV to and from debug registers | 0F | |
Paging
The 386 could do paging:
- 32-to-32 bit address (virtual to physical) translation
- 4K page frames
- two-levels
The page-translation step is optional. Page translation is in effect only when the PG bit of CR0 is set. The paging enabled (PG) bit of CR0 cannot be set until the processor is in protected mode.
31 22 21 12 11 0
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| 10 bits | 10 bits | 12 bits |
+---------------------------------------------------------------+
| DIR-IDX | PAGE-IDX | OFFSET |
1024 1024 4K