Last modified: Sat May 30 11:42:28 UTC+0200 2026 © A. Tarpai

ALU Investigations (PRELIMINARY)

The heart of the ALU since the beginning of microprocessors is the adder.

This is an elaborative analysis of how the binary adder works, how it can be used for subtraction, how the SUB instruction and full signed arithmetic capabilities can be built on top of a relatively simple adder circuit – with implementation details about Intel processors.

Part I.

The adder. Additions and subtractions. SUB instruction in hardware. Intel x86 ADD/SUB and ADC/SBB instructions.

Part II.

Signed arithmetic and the adder. Overflow bit (OF) analysis and detection in hardware by the CY XOR CY_–1 method. Intel x86 CMP instruction and signed comparison

It is one of those I always wondered.. how these really work in microprocessors and how it was done in the early days of computing.

An Intel-style 8-bit adder with flags:

     •---------•---------•---------•---------•---------•---------•---------•-------<---  A[7..0] in
     | •-------|-•-------|-•-------|-•-------|-•-------|-•-------|-•-------|-•-----<---  B[7..0] in
    _|_|_     _|_|_     _|_|_     _|_|_     _|_|_     _|_|_     _|_|_     _|_|_
   | A B |   | A B |   | A B |   | A B |   | A B |   | A B |   | A B |   | A B |
   |    C|_  |    C|_  |    C|_  |    C|_  |    C|_  |    C|_  |    C|_  |    C|_______CARRY in_______
  _|C'   | \_|C'   | \_|C'   | \_|C'   | \_|C'   | \_|C'   | \_|C'   | \_|C'   |                      |
 | |__Y__|  ||__Y__|   |__Y__|   |__Y__|  ||__Y__|   |__Y__|   |__Y__|   |__Y__|                      |
 |    |     |   |         |         |     |   |         |         |         |                         |
 |    |     |   |         |         |     |   |         |         |         |                         |
 |    •-----|---•---------•---------•-----|---•---------•---o-----•---o-----•--------->  Y[7..0] out  |
 |    |     |                             |                 |         |                               |
 •----|----XOR                            |                _|_       _|_                              |
 |    |     |                             |               |   |     |   |                             |
 |    •-XOR-•                             |               |___|     |___|                             |
 |    |  |  |                             |                 |         |                               |
 |    SF |  OF                            AF                ZF        PF                              |
 |      LESS                                                                                          |
 |                                                                                                    |
 |                                                                                                    |
 |                                                                                                    |
 |                  ____                                                                              |
 |__CARRY out______| CF |_____________________________________________________________________________|
                   |____|

• CF: carry_in and carry_out is the same flip-flop, the Carry Flag (CF), wired to the last C'(7) carry out
• AF (Auxiliary Carry) wired to C'(3), carry out on 4 bits, the old 4004 CY flag
• SF (Sign flag) is wired to the last Y(7) output
• ZF (Zero flag) ZF is set when all Y output is zero. Note that a set carry but the result is zero will also set the Zero bit.
• PF (Parity flag) PF is set when there is an EVEN number '1'-s in the result. For a zero result it is SET, considered even.

ZF and PF is derived by combinational logic.

By adding two XOR gates to this simple circuit it becomes a fully fledged signed arithmetic device:

• OF (Signed Overlow Flag) following additions and subtractions
• LESS, the so-called less flag, makes signed comparison possible (this is not a real flag)