Last modified: Sat Jun 20 16:38:53 UTC+0200 2026 © A. Tarpai
Segmentation architecture evolution
16-bit 8086 CPU Hardware model
1MB RAM
+-----------+
| |
| |
+-----------+
| | 16-bit
| 64 KB | <---- OFFSET
segment | |
16-bit 8086 CPU base ----> +-----------+
+---------------------+---------------+ SR x 16 | |
| | on-chip SR | | |
| | ________ | | |
| 16-bit registers | |___CS___| | | |
| | |___DS___| | | |
| | |___SS___| | | |
| 16-bit instr OFFS --|-> |___ES___| | -----------------------/----> | |
| | 16-bit | 20-bit | |
| | | address | |
+---------------------+---------------+ +-----------+
16 x 64KB
The 286 is based on the segmented 8086 model. This architecture is the basis for all following Intel CPU-s:
- DCR with 24-bit BASE
- Protection
16-bit 286 CPU Hardware model
16MB RAM
+-----------+
| |
| |
+-----------+
| | 16-bit
24-bit | 64 KB | <-- OFFSET
segment | |
base -----> +-----------+
| |
___________________________________ | |
| "8086 CPU" | PROTECTION | |
+---------------------+--------------+---------------|---+ | |
| | on-chip SR | | | | |
| | ________ | ___________ _|_ | | |
| 16-bit registers | |___CS___|-|-|___________|___| | | |
| | |___DS___|-|-|___________|___| | | |
| | |___SS___|-|-|___________|___| | | |
| 16-bit instr OFFS --|-> |___ES___|-|-|___________|___| | -----/---> | |
| | 16-bit | 24-bit base | 24-bit | |
| | | | address | |
+---------------------+--------------+-------------------+ +-----------+
256 x 64KB
The 386 is based on the 286 hardware model. This architecture is the IA-32 and kept since then:
- DCR with 32-bit BASE
- Protection
32-bit 386 CPU Hardware model
4GB RAM
+-----------+
| |
| |
| |
| | 32-bit
32-bit | 4GB | <-- OFFSET
segment | |
base -----> +-----------+
| |
| |
| |
| |
32-bit 386 CPU PROTECTION | |
+---------------------+--------------+------------------|---+ | |
| | on-chip SR | | | | |
| | ________ | ______________ _|_ | | |
| 32-bit registers | |___CS___|-|-|______________|___| | | |
| | |___DS___|-|-|______________|___| | | |
| | |___SS___|-|-|______________|___| | | |
| | |___ES___|-|-|______________|___| | | |
| | |___FS___|-|-|______________|___| | | |
| 32-bit instr OFFS --|-> |___GS___|-|-|______________|___| | ----/---> | |
| | 16-bit | 32-bit base | 32-bit | |
| | | | address | |
+---------------------+--------------+----------------------+ +-----------+
Segment adder evolution
Segment registers are fast on-chip adders implementing the segmentation scheme.
Every adder truncates a possible overflow bit, resulting in 1M/24M/4G address wrap-around.
8086 PHYSICAL ADDRESS PATH
19 0 19 0
+---+---------------+ +---------------+---+
| 0 | 16-BIT OFFS | | 16-BIT SR | 0 | 20-BIT "SR BASE"
+---+---------------+ +---------------+---+
| |
| 20-bit adder |
| ___ |
+------------/ + \------------+
\___/
|
A19 | A0
+-------------------+
| |
+-------------------+
20-BIT PHYSICAL
ADDRESS
286 PHYSICAL ADDRESS PATH
23 0 23 0
+---+---+---------------+ +-----------------------+
| 0 | 0 | 16-BIT OFFS | | 24-BIT SR BASE |
+---+---+---------------+ +-----------------------+
| |
LIMIT/ACCESS |
CHECK |
| 24-bit adder |
| ___ |
+------------/ + \------------+
\___/
|
A23 | A0
+-----------------------+
| |
+-----------------------+
24-BIT PHYSICAL
ADDRESS
386 PHYSICAL ADDRESS PATH
31 0 31 0
+-------------------------------+ +-------------------------------+
| 32-BIT OFFS | | 32-BIT SR BASE |
+-------------------------------+ +-------------------------------+
| |
LIMIT/ACCESS |
CHECK |
| 32-bit adder |
| ___ |
+------------/ + \------------+
\___/
|
A31 | A0
+-------------------------------+
| |
+-------------------------------+
32-BIT PHYSICAL
ADDRESS*
* Still virtual when paging enabled