Last modified: Mon Feb 11 08:57:02 UTC+0100 2019 © A. Tarpai
Programming the SPEA board
© A. Tarpai (tarpai76 gmail) 2019
Previously, I was interested in hooking up ATI-TV ISA to an S3 ViRGE/DX board and display live video from a DVD player. Well, it didn't go very smooth, especially when it comes to hardware and connections. Then I've found this beautiful piece of hardware, a graphics- video-digitizer combo board built around S3 Trio64V+ and Bt819A. Here at least everything is already connected, all we have to do is programming. Well, almost.
Spea Software AG Mirage Video TV
A SPEA1/V7 - MIRAGE VIDEO TV, designed and built in 1994(?). Following the story line below, the DIAMOND sticker over the Spea Software AG inscription, possibly (I don't want to remove the sticker - yet).
Analyzing the SPEA board
It's easy to see the 16-bit digital video path between S3 Trio64V+ and Bt819A. One reason I actually bought this board. (There is also TV-TUNER, Teletext decoder on it, but I save this for later programming projects. The purpose here is to get composite-video into Bt819A from a DVD-player, send it to Trio64V+ and display it.)
I took a few hi-res photos and started to discover the board's connections with a digital multimeter.
What we have:
- S3 Trio64V+
- Bt819A video digitizer
- GAL16V8B PLD
- SAA5246A Teletext decoder
- 32K SRAM for Teletext
- 2M DRAM
- VGA BIOS
- 35.47 MHz PAL clock
- 28.64 MHz NTSC clock
- 14.8 MHz VGA clock
- TV-TUNER
- 27 MHz Teletext clock
- J3 34-pin LPB connector
- J6 header for power, INTA, RESET (Scenic/MX2?)
- J5 external audio header (Sonic/AD?)
- 74HCT125D Quad buffer/line driver
- CD4052B channel multiplexer (for I2C)
- CD4052B channel multiplexer (for audio)
- NE555D Precision Timer
- TDA1308 stereo headphone driver
- VGA out
- audio out
- Composite/S-video in
- Cable in
The circled area is the 16-bit data path between Bt819A and Trio64V+.
GAL16V8B PLD
GAL16V8B is a programmable logic device from Lattice Semiconductor. That was bad news for my project: exactly what was obscure got even more obscure. After identifying pins and connections it seemed like the purpose of the logic is to drive VS/HS/LCLK for Trio64V+ based on a bunch of video timing inputs from Bt819.
GAL in/out
Bt
--> HRESET
--> VRESET Example wiring for HS
--> ACTIVE
--> FIELD . . . . . . . . . . . . . . . . LPB
--> DVALID . . . . . . . . . . . . . . . . connector
--> QCLK |
--> CLKx1 +-- 4.7KΩ -- Vcc
<-- OE HS |
|
Trio +-- 470Ω -- GAL -- Bt
--> HS |
--> VS |
--> LCLK +-- 470Ω -- Trio
<-- GOP0
<-- GOP1
CD4052B AUDIO
--> INH
The GAL also drives Bt819A's OE# pin, which is not active after reset. The 2 inputs from Trio64V+, GOP0 and GOP1 are high after reset. I tried all combinations and GAL kicks in when GOP_1_0 = 10: it asserts OE#, the Bt819A timing- and data pins emerge from 3-state, then GAL starts to drive HS/VS/LCLK for Trio64V+. This is how to switch on Bt819A.
In the meantime I bought a Saleae logic analyzer to investigate GAL and the HS/VS/CLCK output.
GAL and VSYNC
When it comes to fields of video data the results were interesting: GAL outputs VS @ 30Hz (and not 60Hz), skipping every other field, while Bt819A outputs individual fields separated by VRESET:
Spea solved the de-interlacing problem by simply dropping every even field sent to Trio64V+, which means also losing half of vertical resolution. An elegant solution: 30 x 240-lines half-frames per sec gives nice motion, enough resolution (we're in 1995) and are better than those horrible interlace-combs. Trio64V+ has no de-interlacing function at all (apart from that LPB can also skip every other fields, see MMFF00_25?).
When the LPB window is increased vertically beyond 240 lines, the even field reveals at the bottom and is different from the odd field. Video out froma a Canon Powershot A590 connected to Spea composite-in:
Bypassing the GAL and interlaced
I still wanted to get full vertical resolution out of Bt819A somehow, but from the GAL's VS-signal it's impossible to interlace the two fields for Trio64V+. So I experimented bypassing the GAL. There was one big problem: only GAL can assert OE# for Bt819A, but GAL must be enabled for this, setting GOP[1..0]= 10 and will also drive HS/VS/CLCK lines in the same time. I really didn't want to, but desoldered the OE# pin..
Then with GAL disabled I tried many Bt819A video timing pins to connect to Trio64V+: HRESET, ACTIVE, VRESET, DVALID, CLKx1 and QCLK right from Bt819A. I used GAL-pins as connection-points, holes on the board, and many trials changing the code.
The Trio64V+ code has been changed to use double-buffers and fill every other lines after VS occurence (VRESET → VS). Horizontal scaling is the same, around 330 pixels. The LPB window height is the same (240 lines), but the FB filled interlaced from alternating fields:
Not bad. For still pictures. The problem with alternating fields is that there is no way to know which one is odd or even for Trio64V+. When lucky, we interlace the right ones. When unlucky, we interlace opposite. The last line of the odd field ends in the middle, and the even field starts with a half-line. This will most likely confuse Trio64V+ and messes up the screen (skips the first line or the first line runs beyond the right edge).
I guess that's why results varied, clearly seen on this paused DVD frame. Depending on when the first VS came, Trio64V+ locked to even or odd field as the first:
The good (lucky one): 
The unlucky one: 
odd even odd odd even odd even
__________ __________ __________ __________ __________ __________ __________
| -------- | | ~~~~ | | -------- | | -------- | | ~~~~ | | -------- | | ~~~~ |
| -------- | | ~~~~~~~~ | | -------- | | -------- | | ~~~~~~~~ | | -------- | | ~~~~~~~~ |
|_---______| |_~~~~~~~~_| |_---______| |_---______| |_~~~~~~~~_| |_---______| |_~~~~~~~~_|
| | | |
+-------------+ +-------------+
_____|____ _____|____
| ~~~~ | | -------- |
| -------- | proper | ~~~~ | will be
| ~~~~~~~~ | interlacing | -------- | wrong
| -------- | | ~~~~~~~~ |
| ~~~~~~~~ | | --- |
| --- | | ~~~~~~~~ |
|__________| |__________|
The analog video signal does differentiates between the two: the signal pattern in the vertical synchronization period is different. Bt819A indicates field parity on the FIELD pin, but Trio64V+ cannot make any use of it - unfortunately.
When playing the DVD, well, I can confirm that the interlace-artifacts were awful..
, 
NE555D Precision Timer
"These devices are precision timing circuits capable of producing accurate time delays or oscillation." (Ti, STMicroelectronics, STMicroelectronics)
- ^Spea Software AG A company from Bayern, Germany, established in 1985. Buys Video Seven, US CA, in May 1993 (SPEA/V7 products). Videoseven has been developing and marketing graphics cards and software since 1983. Video Seven is bankrupt in the same year, July 1993. Diamond Multimedia obtains Spea in November 1995.